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256 lines
3.9 KiB
256 lines
3.9 KiB
update=Sat 20 Jun 2020 09:31:19 AM EDT |
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version=1 |
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last_client=kicad |
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[general] |
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version=1 |
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RootSch= |
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BoardNm= |
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[cvpcb] |
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version=1 |
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NetIExt=net |
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[eeschema] |
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version=1 |
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LibDir= |
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[eeschema/libraries] |
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[pcbnew] |
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version=1 |
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PageLayoutDescrFile= |
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LastNetListRead=BreadBatt.net |
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CopperLayerCount=2 |
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BoardThickness=1.6002 |
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AllowMicroVias=0 |
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AllowBlindVias=0 |
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RequireCourtyardDefinitions=0 |
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ProhibitOverlappingCourtyards=1 |
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MinTrackWidth=0.1524 |
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MinViaDiameter=0.508 |
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MinViaDrill=0.3048 |
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MinMicroViaDiameter=0.2 |
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MinMicroViaDrill=0.09999999999999999 |
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MinHoleToHole=0.25 |
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TrackWidth1=0.1524 |
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TrackWidth2=0.1524 |
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TrackWidth3=0.2032 |
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TrackWidth4=0.254 |
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TrackWidth5=0.508 |
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TrackWidth6=0.762 |
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TrackWidth7=1.016 |
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TrackWidth8=1.27 |
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TrackWidth9=1.524 |
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ViaDiameter1=0.508 |
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ViaDrill1=0.3048 |
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dPairWidth1=0.2 |
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dPairGap1=0.25 |
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dPairViaGap1=0.25 |
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SilkLineWidth=0.15 |
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SilkTextSizeV=1 |
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SilkTextSizeH=1 |
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SilkTextSizeThickness=0.15 |
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SilkTextItalic=0 |
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SilkTextUpright=1 |
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CopperLineWidth=0.2 |
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CopperTextSizeV=1.5 |
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CopperTextSizeH=1.5 |
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CopperTextThickness=0.3 |
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CopperTextItalic=0 |
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CopperTextUpright=1 |
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EdgeCutLineWidth=0.0254 |
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CourtyardLineWidth=0.05 |
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OthersLineWidth=0.15 |
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OthersTextSizeV=1 |
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OthersTextSizeH=1 |
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OthersTextSizeThickness=0.15 |
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OthersTextItalic=0 |
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OthersTextUpright=1 |
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SolderMaskClearance=0.0508 |
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SolderMaskMinWidth=0.254 |
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SolderPasteClearance=0 |
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SolderPasteRatio=0 |
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[pcbnew/Layer.F.Cu] |
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Name=F.Cu |
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Type=0 |
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Enabled=1 |
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[pcbnew/Layer.In1.Cu] |
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Name=In1.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In2.Cu] |
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Name=In2.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In3.Cu] |
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Name=In3.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In4.Cu] |
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Name=In4.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In5.Cu] |
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Name=In5.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In6.Cu] |
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Name=In6.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In7.Cu] |
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Name=In7.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In8.Cu] |
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Name=In8.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In9.Cu] |
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Name=In9.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In10.Cu] |
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Name=In10.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In11.Cu] |
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Name=In11.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In12.Cu] |
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Name=In12.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In13.Cu] |
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Name=In13.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In14.Cu] |
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Name=In14.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In15.Cu] |
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Name=In15.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In16.Cu] |
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Name=In16.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In17.Cu] |
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Name=In17.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In18.Cu] |
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Name=In18.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In19.Cu] |
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Name=In19.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In20.Cu] |
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Name=In20.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In21.Cu] |
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Name=In21.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In22.Cu] |
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Name=In22.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In23.Cu] |
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Name=In23.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In24.Cu] |
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Name=In24.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In25.Cu] |
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Name=In25.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In26.Cu] |
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Name=In26.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In27.Cu] |
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Name=In27.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In28.Cu] |
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Name=In28.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In29.Cu] |
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Name=In29.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.In30.Cu] |
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Name=In30.Cu |
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Type=0 |
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Enabled=0 |
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[pcbnew/Layer.B.Cu] |
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Name=B.Cu |
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Type=0 |
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Enabled=1 |
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[pcbnew/Layer.B.Adhes] |
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Enabled=1 |
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[pcbnew/Layer.F.Adhes] |
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Enabled=1 |
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[pcbnew/Layer.B.Paste] |
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Enabled=1 |
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[pcbnew/Layer.F.Paste] |
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Enabled=1 |
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[pcbnew/Layer.B.SilkS] |
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Enabled=1 |
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[pcbnew/Layer.F.SilkS] |
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Enabled=1 |
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[pcbnew/Layer.B.Mask] |
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Enabled=1 |
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[pcbnew/Layer.F.Mask] |
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Enabled=1 |
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[pcbnew/Layer.Dwgs.User] |
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Enabled=1 |
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[pcbnew/Layer.Cmts.User] |
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Enabled=1 |
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[pcbnew/Layer.Eco1.User] |
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Enabled=1 |
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[pcbnew/Layer.Eco2.User] |
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Enabled=1 |
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[pcbnew/Layer.Edge.Cuts] |
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Enabled=1 |
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[pcbnew/Layer.Margin] |
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Enabled=1 |
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[pcbnew/Layer.B.CrtYd] |
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Enabled=1 |
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[pcbnew/Layer.F.CrtYd] |
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Enabled=1 |
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[pcbnew/Layer.B.Fab] |
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Enabled=1 |
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[pcbnew/Layer.F.Fab] |
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Enabled=1 |
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[pcbnew/Layer.Rescue] |
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Enabled=0 |
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[pcbnew/Netclasses] |
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[pcbnew/Netclasses/Default] |
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Name=Default |
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Clearance=0.1524 |
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TrackWidth=0.1524 |
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ViaDiameter=0.508 |
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ViaDrill=0.3048 |
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uViaDiameter=0.3 |
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uViaDrill=0.1 |
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dPairWidth=0.2 |
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dPairGap=0.25 |
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dPairViaGap=0.25 |
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[schematic_editor] |
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version=1 |
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PageLayoutDescrFile= |
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PlotDirectoryName=PDFs |
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SubpartIdSeparator=0 |
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SubpartFirstId=65 |
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NetFmtName=Pcbnew |
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SpiceAjustPassiveValues=0 |
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LabSize=50 |
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ERC_TestSimilarLabels=1
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