Mateusz Salamon
5 years ago
128 changed files with 35429 additions and 24506 deletions
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/**
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****************************************************************************** |
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* File Name : dma.h |
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* Description : This file contains all the function prototypes for |
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* the dma.c file |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under Ultimate Liberty license |
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* SLA0044, the "License"; You may not use this file except in compliance with |
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* the License. You may obtain a copy of the License at: |
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* www.st.com/SLA0044 |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __dma_H |
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#define __dma_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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/* DMA memory to memory transfer handles -------------------------------------*/ |
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/* USER CODE BEGIN Includes */ |
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/* USER CODE END Includes */ |
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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void MX_DMA_Init(void); |
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/* USER CODE BEGIN Prototypes */ |
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/* USER CODE END Prototypes */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __dma_H */ |
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/**
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/**
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****************************************************************************** |
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* File Name : gpio.h |
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* Description : This file contains all the functions prototypes for
|
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* the gpio
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under Ultimate Liberty license |
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* SLA0044, the "License"; You may not use this file except in compliance with |
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* the License. You may obtain a copy of the License at: |
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* www.st.com/SLA0044 |
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* |
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****************************************************************************** |
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*/ |
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|
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __gpio_H |
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#define __gpio_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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|
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/* USER CODE BEGIN Includes */ |
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|
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/* USER CODE END Includes */ |
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|
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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void MX_GPIO_Init(void); |
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/* USER CODE BEGIN Prototypes */ |
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/* USER CODE END Prototypes */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__ pinoutConfig_H */ |
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|
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/**
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* @} |
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*/ |
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|
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/**
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* @} |
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*/ |
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|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/* USER CODE BEGIN Header */ |
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/**
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****************************************************************************** |
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* @file : main.h |
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* @brief : Header for main.c file. |
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* This file contains the common defines of the application. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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|
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __MAIN_H |
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#define __MAIN_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f1xx_hal.h" |
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|
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/* Private includes ----------------------------------------------------------*/ |
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/* USER CODE BEGIN Includes */ |
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|
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/* USER CODE END Includes */ |
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|
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/* Exported types ------------------------------------------------------------*/ |
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/* USER CODE BEGIN ET */ |
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|
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/* USER CODE END ET */ |
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|
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/* Exported constants --------------------------------------------------------*/ |
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/* USER CODE BEGIN EC */ |
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/* USER CODE END EC */ |
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|
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/* Exported macro ------------------------------------------------------------*/ |
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/* USER CODE BEGIN EM */ |
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|
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/* USER CODE END EM */ |
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|
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/* Exported functions prototypes ---------------------------------------------*/ |
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void Error_Handler(void); |
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/* USER CODE BEGIN EFP */ |
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/* USER CODE END EFP */ |
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/* Private defines -----------------------------------------------------------*/ |
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#define LED_Pin GPIO_PIN_13 |
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#define LED_GPIO_Port GPIOC |
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#define TEST_Pin GPIO_PIN_0 |
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#define TEST_GPIO_Port GPIOA |
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/* USER CODE BEGIN Private defines */ |
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|
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/* USER CODE END Private defines */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __MAIN_H */ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/**
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****************************************************************************** |
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* File Name : SPI.h |
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* Description : This file provides code for the configuration |
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* of the SPI instances. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under Ultimate Liberty license |
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* SLA0044, the "License"; You may not use this file except in compliance with |
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* the License. You may obtain a copy of the License at: |
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* www.st.com/SLA0044 |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __spi_H |
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#define __spi_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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/* USER CODE BEGIN Includes */ |
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|
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/* USER CODE END Includes */ |
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extern SPI_HandleTypeDef hspi1; |
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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void MX_SPI1_Init(void); |
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/* USER CODE BEGIN Prototypes */ |
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|
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/* USER CODE END Prototypes */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__ spi_H */ |
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/**
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* @} |
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*/ |
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|
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/**
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/* USER CODE BEGIN Header */ |
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/**
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****************************************************************************** |
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* @file stm32f1xx_it.h |
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* @brief This file contains the headers of the interrupt handlers. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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|
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F1xx_IT_H |
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#define __STM32F1xx_IT_H |
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|
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Private includes ----------------------------------------------------------*/ |
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/* USER CODE BEGIN Includes */ |
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|
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/* USER CODE END Includes */ |
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|
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/* Exported types ------------------------------------------------------------*/ |
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/* USER CODE BEGIN ET */ |
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|
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/* USER CODE END ET */ |
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|
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/* Exported constants --------------------------------------------------------*/ |
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/* USER CODE BEGIN EC */ |
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|
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/* USER CODE END EC */ |
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|
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/* Exported macro ------------------------------------------------------------*/ |
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/* USER CODE BEGIN EM */ |
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|
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/* USER CODE END EM */ |
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|
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/* Exported functions prototypes ---------------------------------------------*/ |
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void NMI_Handler(void); |
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void HardFault_Handler(void); |
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void MemManage_Handler(void); |
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void BusFault_Handler(void); |
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void UsageFault_Handler(void); |
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void SVC_Handler(void); |
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void DebugMon_Handler(void); |
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void PendSV_Handler(void); |
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void SysTick_Handler(void); |
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void DMA1_Channel3_IRQHandler(void); |
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void USB_LP_CAN1_RX0_IRQHandler(void); |
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/* USER CODE BEGIN EFP */ |
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|
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/* USER CODE END EFP */ |
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|
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#ifdef __cplusplus |
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} |
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#endif |
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|
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#endif /* __STM32F1xx_IT_H */ |
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|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@@ -0,0 +1,63 @@
|
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/**
|
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****************************************************************************** |
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* File Name : dma.c |
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* Description : This file provides code for the configuration |
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* of all the requested memory to memory DMA transfers. |
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****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under Ultimate Liberty license |
||||
* SLA0044, the "License"; You may not use this file except in compliance with |
||||
* the License. You may obtain a copy of the License at: |
||||
* www.st.com/SLA0044 |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
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/* Includes ------------------------------------------------------------------*/ |
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#include "dma.h" |
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|
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/* USER CODE BEGIN 0 */ |
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|
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/* USER CODE END 0 */ |
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|
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/*----------------------------------------------------------------------------*/ |
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/* Configure DMA */ |
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/*----------------------------------------------------------------------------*/ |
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/* USER CODE BEGIN 1 */ |
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/* USER CODE END 1 */ |
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/**
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* Enable DMA controller clock |
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*/ |
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void MX_DMA_Init(void)
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{ |
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/* DMA controller clock enable */ |
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__HAL_RCC_DMA1_CLK_ENABLE(); |
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/* DMA interrupt init */ |
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/* DMA1_Channel3_IRQn interrupt configuration */ |
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HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 1, 0); |
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HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); |
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} |
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|
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/* USER CODE BEGIN 2 */ |
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/* USER CODE END 2 */ |
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|
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/**
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* @} |
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*/ |
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|
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/**
|
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* @} |
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*/ |
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|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@@ -0,0 +1,76 @@
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/**
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****************************************************************************** |
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* File Name : gpio.c |
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* Description : This file provides code for the configuration |
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* of all used GPIO pins. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under Ultimate Liberty license |
||||
* SLA0044, the "License"; You may not use this file except in compliance with |
||||
* the License. You may obtain a copy of the License at: |
||||
* www.st.com/SLA0044 |
||||
* |
||||
****************************************************************************** |
||||
*/ |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "gpio.h" |
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/* USER CODE BEGIN 0 */ |
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/* USER CODE END 0 */ |
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/*----------------------------------------------------------------------------*/ |
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/* Configure GPIO */ |
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/*----------------------------------------------------------------------------*/ |
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/* USER CODE BEGIN 1 */ |
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/* USER CODE END 1 */ |
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|
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/** Configure pins as
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* Analog
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* Input
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* Output |
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* EVENT_OUT |
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* EXTI |
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*/ |
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void MX_GPIO_Init(void) |
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{ |
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GPIO_InitTypeDef GPIO_InitStruct = {0}; |
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/* GPIO Ports Clock Enable */ |
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__HAL_RCC_GPIOC_CLK_ENABLE(); |
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__HAL_RCC_GPIOD_CLK_ENABLE(); |
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__HAL_RCC_GPIOA_CLK_ENABLE(); |
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/*Configure GPIO pin Output Level */ |
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HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); |
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/*Configure GPIO pin Output Level */ |
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HAL_GPIO_WritePin(TEST_GPIO_Port, TEST_Pin, GPIO_PIN_RESET); |
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/*Configure GPIO pin : PtPin */ |
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GPIO_InitStruct.Pin = LED_Pin; |
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; |
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GPIO_InitStruct.Pull = GPIO_NOPULL; |
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; |
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HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); |
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/*Configure GPIO pin : PtPin */ |
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GPIO_InitStruct.Pin = TEST_Pin; |
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; |
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GPIO_InitStruct.Pull = GPIO_NOPULL; |
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; |
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HAL_GPIO_Init(TEST_GPIO_Port, &GPIO_InitStruct); |
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} |
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/* USER CODE BEGIN 2 */ |
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/* USER CODE END 2 */ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/* USER CODE BEGIN Header */ |
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/**
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****************************************************************************** |
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* File Name : stm32f1xx_hal_msp.c |
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* Description : This file provides code for the MSP Initialization
|
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* and de-Initialization codes. |
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****************************************************************************** |
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* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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/* USER CODE BEGIN Includes */ |
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|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
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/* USER CODE BEGIN TD */ |
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|
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/* USER CODE END TD */ |
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|
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/* Private define ------------------------------------------------------------*/ |
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/* USER CODE BEGIN Define */ |
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|
||||
/* USER CODE END Define */ |
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|
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/* Private macro -------------------------------------------------------------*/ |
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/* USER CODE BEGIN Macro */ |
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|
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/* USER CODE END Macro */ |
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|
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/* Private variables ---------------------------------------------------------*/ |
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/* USER CODE BEGIN PV */ |
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|
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/* USER CODE END PV */ |
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|
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/* Private function prototypes -----------------------------------------------*/ |
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/* USER CODE BEGIN PFP */ |
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|
||||
/* USER CODE END PFP */ |
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|
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/* External functions --------------------------------------------------------*/ |
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/* USER CODE BEGIN ExternalFunctions */ |
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|
||||
/* USER CODE END ExternalFunctions */ |
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|
||||
/* USER CODE BEGIN 0 */ |
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|
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/* USER CODE END 0 */ |
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/**
|
||||
* Initializes the Global MSP. |
||||
*/ |
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void HAL_MspInit(void) |
||||
{ |
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/* USER CODE BEGIN MspInit 0 */ |
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|
||||
/* USER CODE END MspInit 0 */ |
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|
||||
__HAL_RCC_AFIO_CLK_ENABLE(); |
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__HAL_RCC_PWR_CLK_ENABLE(); |
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|
||||
/* System interrupt init*/ |
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|
||||
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
||||
*/ |
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__HAL_AFIO_REMAP_SWJ_NOJTAG(); |
||||
|
||||
/* USER CODE BEGIN MspInit 1 */ |
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|
||||
/* USER CODE END MspInit 1 */ |
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} |
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|
||||
/* USER CODE BEGIN 1 */ |
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|
||||
/* USER CODE END 1 */ |
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|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@@ -0,0 +1,159 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file syscalls.c |
||||
* @author Auto-generated by STM32CubeIDE |
||||
* @brief STM32CubeIDE Minimal System calls file |
||||
* |
||||
* For more information about which c-functions |
||||
* need which of these lowlevel functions |
||||
* please consult the Newlib libc-manual |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes */ |
||||
#include <sys/stat.h> |
||||
#include <stdlib.h> |
||||
#include <errno.h> |
||||
#include <stdio.h> |
||||
#include <signal.h> |
||||
#include <time.h> |
||||
#include <sys/time.h> |
||||
#include <sys/times.h> |
||||
|
||||
|
||||
/* Variables */ |
||||
//#undef errno
|
||||
extern int errno; |
||||
extern int __io_putchar(int ch) __attribute__((weak)); |
||||
extern int __io_getchar(void) __attribute__((weak)); |
||||
|
||||
register char * stack_ptr asm("sp"); |
||||
|
||||
char *__env[1] = { 0 }; |
||||
char **environ = __env; |
||||
|
||||
|
||||
/* Functions */ |
||||
void initialise_monitor_handles() |
||||
{ |
||||
} |
||||
|
||||
int _getpid(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int _kill(int pid, int sig) |
||||
{ |
||||
errno = EINVAL; |
||||
return -1; |
||||
} |
||||
|
||||
void _exit (int status) |
||||
{ |
||||
_kill(status, -1); |
||||
while (1) {} /* Make sure we hang here */ |
||||
} |
||||
|
||||
__attribute__((weak)) int _read(int file, char *ptr, int len) |
||||
{ |
||||
int DataIdx; |
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++) |
||||
{ |
||||
*ptr++ = __io_getchar(); |
||||
} |
||||
|
||||
return len; |
||||
} |
||||
|
||||
__attribute__((weak)) int _write(int file, char *ptr, int len) |
||||
{ |
||||
int DataIdx; |
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++) |
||||
{ |
||||
__io_putchar(*ptr++); |
||||
} |
||||
return len; |
||||
} |
||||
|
||||
int _close(int file) |
||||
{ |
||||
return -1; |
||||
} |
||||
|
||||
|
||||
int _fstat(int file, struct stat *st) |
||||
{ |
||||
st->st_mode = S_IFCHR; |
||||
return 0; |
||||
} |
||||
|
||||
int _isatty(int file) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int _lseek(int file, int ptr, int dir) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int _open(char *path, int flags, ...) |
||||
{ |
||||
/* Pretend like we always fail */ |
||||
return -1; |
||||
} |
||||
|
||||
int _wait(int *status) |
||||
{ |
||||
errno = ECHILD; |
||||
return -1; |
||||
} |
||||
|
||||
int _unlink(char *name) |
||||
{ |
||||
errno = ENOENT; |
||||
return -1; |
||||
} |
||||
|
||||
int _times(struct tms *buf) |
||||
{ |
||||
return -1; |
||||
} |
||||
|
||||
int _stat(char *file, struct stat *st) |
||||
{ |
||||
st->st_mode = S_IFCHR; |
||||
return 0; |
||||
} |
||||
|
||||
int _link(char *old, char *new) |
||||
{ |
||||
errno = EMLINK; |
||||
return -1; |
||||
} |
||||
|
||||
int _fork(void) |
||||
{ |
||||
errno = EAGAIN; |
||||
return -1; |
||||
} |
||||
|
||||
int _execve(char *name, char **argv, char **env) |
||||
{ |
||||
errno = ENOMEM; |
||||
return -1; |
||||
} |
||||
@ -0,0 +1,58 @@
@@ -0,0 +1,58 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file sysmem.c |
||||
* @author Auto-generated by STM32CubeIDE |
||||
* @brief STM32CubeIDE Minimal System Memory calls file |
||||
* |
||||
* For more information about which c-functions |
||||
* need which of these lowlevel functions |
||||
* please consult the Newlib libc-manual |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes */ |
||||
#include <errno.h> |
||||
#include <stdio.h> |
||||
|
||||
/* Variables */ |
||||
extern int errno; |
||||
register char * stack_ptr asm("sp"); |
||||
|
||||
/* Functions */ |
||||
|
||||
/**
|
||||
_sbrk |
||||
Increase program data space. Malloc and related functions depend on this |
||||
**/ |
||||
caddr_t _sbrk(int incr) |
||||
{ |
||||
extern char end asm("end"); |
||||
static char *heap_end; |
||||
char *prev_heap_end; |
||||
|
||||
if (heap_end == 0) |
||||
heap_end = &end; |
||||
|
||||
prev_heap_end = heap_end; |
||||
if (heap_end + incr > stack_ptr) |
||||
{ |
||||
errno = ENOMEM; |
||||
return (caddr_t) -1; |
||||
} |
||||
|
||||
heap_end += incr; |
||||
|
||||
return (caddr_t) prev_heap_end; |
||||
} |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,136 +0,0 @@
@@ -1,136 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. October 2015 |
||||
* $Revision: V.1.4.5 a |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_common_tables.h |
||||
* |
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H |
||||
#define _ARM_COMMON_TABLES_H |
||||
|
||||
#include "arm_math.h" |
||||
|
||||
extern const uint16_t armBitRevTable[1024]; |
||||
extern const q15_t armRecipTableQ15[64]; |
||||
extern const q31_t armRecipTableQ31[64]; |
||||
/* extern const q31_t realCoefAQ31[1024]; */ |
||||
/* extern const q31_t realCoefBQ31[1024]; */ |
||||
extern const float32_t twiddleCoef_16[32]; |
||||
extern const float32_t twiddleCoef_32[64]; |
||||
extern const float32_t twiddleCoef_64[128]; |
||||
extern const float32_t twiddleCoef_128[256]; |
||||
extern const float32_t twiddleCoef_256[512]; |
||||
extern const float32_t twiddleCoef_512[1024]; |
||||
extern const float32_t twiddleCoef_1024[2048]; |
||||
extern const float32_t twiddleCoef_2048[4096]; |
||||
extern const float32_t twiddleCoef_4096[8192]; |
||||
#define twiddleCoef twiddleCoef_4096 |
||||
extern const q31_t twiddleCoef_16_q31[24]; |
||||
extern const q31_t twiddleCoef_32_q31[48]; |
||||
extern const q31_t twiddleCoef_64_q31[96]; |
||||
extern const q31_t twiddleCoef_128_q31[192]; |
||||
extern const q31_t twiddleCoef_256_q31[384]; |
||||
extern const q31_t twiddleCoef_512_q31[768]; |
||||
extern const q31_t twiddleCoef_1024_q31[1536]; |
||||
extern const q31_t twiddleCoef_2048_q31[3072]; |
||||
extern const q31_t twiddleCoef_4096_q31[6144]; |
||||
extern const q15_t twiddleCoef_16_q15[24]; |
||||
extern const q15_t twiddleCoef_32_q15[48]; |
||||
extern const q15_t twiddleCoef_64_q15[96]; |
||||
extern const q15_t twiddleCoef_128_q15[192]; |
||||
extern const q15_t twiddleCoef_256_q15[384]; |
||||
extern const q15_t twiddleCoef_512_q15[768]; |
||||
extern const q15_t twiddleCoef_1024_q15[1536]; |
||||
extern const q15_t twiddleCoef_2048_q15[3072]; |
||||
extern const q15_t twiddleCoef_4096_q15[6144]; |
||||
extern const float32_t twiddleCoef_rfft_32[32]; |
||||
extern const float32_t twiddleCoef_rfft_64[64]; |
||||
extern const float32_t twiddleCoef_rfft_128[128]; |
||||
extern const float32_t twiddleCoef_rfft_256[256]; |
||||
extern const float32_t twiddleCoef_rfft_512[512]; |
||||
extern const float32_t twiddleCoef_rfft_1024[1024]; |
||||
extern const float32_t twiddleCoef_rfft_2048[2048]; |
||||
extern const float32_t twiddleCoef_rfft_4096[4096]; |
||||
|
||||
|
||||
/* floating-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) |
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) |
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) |
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) |
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) |
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) |
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) |
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; |
||||
|
||||
/* fixed-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) |
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; |
||||
|
||||
/* Tables for Fast Math Sine and Cosine */ |
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; |
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */ |
||||
@ -1,79 +0,0 @@
@@ -1,79 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. March 2015 |
||||
* $Revision: V.1.4.5 |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_const_structs.h |
||||
* |
||||
* Description: This file has constant structs that are initialized for |
||||
* user convenience. For example, some can be given as |
||||
* arguments to the arm_cfft_f32() function. |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H |
||||
#define _ARM_CONST_STRUCTS_H |
||||
|
||||
#include "arm_math.h" |
||||
#include "arm_common_tables.h" |
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; |
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; |
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,266 @@
@@ -0,0 +1,266 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h |
||||
* @brief CMSIS compiler generic header file |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#ifndef __CMSIS_COMPILER_H |
||||
#define __CMSIS_COMPILER_H |
||||
|
||||
#include <stdint.h> |
||||
|
||||
/*
|
||||
* Arm Compiler 4/5 |
||||
*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang) |
||||
*/ |
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armclang.h" |
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler |
||||
*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler |
||||
*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iccarm.h> |
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler |
||||
*/ |
||||
#elif defined ( __TI_ARM__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
#define __NO_RETURN __attribute__((noreturn)) |
||||
#endif |
||||
#ifndef __USED |
||||
#define __USED __attribute__((used)) |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __attribute__((weak)) |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED __attribute__((packed)) |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT struct __attribute__((packed)) |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION union __attribute__((packed)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler |
||||
*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
#define __NO_RETURN __attribute__((noreturn)) |
||||
#endif |
||||
#ifndef __USED |
||||
#define __USED __attribute__((used)) |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __attribute__((weak)) |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED __packed__ |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT struct __packed__ |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION union __packed__ |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
struct __packed__ T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#define __ALIGNED(x) __align(x) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler |
||||
*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM _asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN |
||||
#endif |
||||
#ifndef __USED |
||||
#warning No compiler specific solution for __USED. __USED is ignored. |
||||
#define __USED |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __weak |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED @packed |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT @packed struct |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION @packed union |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
@packed struct T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. |
||||
#define __ALIGNED(x) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
#else |
||||
#error Unknown compiler. |
||||
#endif |
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,935 @@
@@ -0,0 +1,935 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h |
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file |
||||
* @version V5.0.7 |
||||
* @date 19. June 2018 |
||||
******************************************************************************/ |
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__ |
||||
#define __CMSIS_ICCARM_H__ |
||||
|
||||
#ifndef __ICCARM__ |
||||
#error This file should only be compiled by ICCARM |
||||
#endif |
||||
|
||||
#pragma system_include |
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic |
||||
|
||||
#if (__VER__ >= 8000000) |
||||
#define __ICCARM_V8 1 |
||||
#else |
||||
#define __ICCARM_V8 0 |
||||
#endif |
||||
|
||||
#ifndef __ALIGNED |
||||
#if __ICCARM_V8 |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#elif (__VER__ >= 7080000) |
||||
/* Needs IAR language extensions */ |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#else |
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. |
||||
#define __ALIGNED(x) |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/ |
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ |
||||
/* Macros already defined */ |
||||
#else |
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#elif defined(__ARM8M_BASELINE__) |
||||
#define __ARM_ARCH_8M_BASE__ 1 |
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' |
||||
#if __ARM_ARCH == 6 |
||||
#define __ARM_ARCH_6M__ 1 |
||||
#elif __ARM_ARCH == 7 |
||||
#if __ARM_FEATURE_DSP |
||||
#define __ARM_ARCH_7EM__ 1 |
||||
#else |
||||
#define __ARM_ARCH_7M__ 1 |
||||
#endif |
||||
#endif /* __ARM_ARCH */ |
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */ |
||||
#endif |
||||
|
||||
/* Alternativ core deduction for older ICCARM's */ |
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ |
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) |
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__) |
||||
#define __ARM_ARCH_6M__ 1 |
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) |
||||
#define __ARM_ARCH_7M__ 1 |
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) |
||||
#define __ARM_ARCH_7EM__ 1 |
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) |
||||
#define __ARM_ARCH_8M_BASE__ 1 |
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#else |
||||
#error "Unknown target." |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 |
||||
#define __IAR_M0_FAMILY 1 |
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 |
||||
#define __IAR_M0_FAMILY 1 |
||||
#else |
||||
#define __IAR_M0_FAMILY 0 |
||||
#endif |
||||
|
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
|
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
|
||||
#ifndef __NO_RETURN |
||||
#if __ICCARM_V8 |
||||
#define __NO_RETURN __attribute__((__noreturn__)) |
||||
#else |
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn") |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED |
||||
#if __ICCARM_V8 |
||||
#define __PACKED __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED __packed |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED_STRUCT |
||||
#if __ICCARM_V8 |
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED_STRUCT __packed struct |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED_UNION |
||||
#if __ICCARM_V8 |
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED_UNION __packed union |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __RESTRICT |
||||
#define __RESTRICT __restrict |
||||
#endif |
||||
|
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
|
||||
#ifndef __FORCEINLINE |
||||
#define __FORCEINLINE _Pragma("inline=forced") |
||||
#endif |
||||
|
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr) |
||||
{ |
||||
return *(__packed uint16_t*)(ptr); |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) |
||||
#endif |
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) |
||||
{ |
||||
*(__packed uint16_t*)(ptr) = val;; |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr) |
||||
{ |
||||
return *(__packed uint32_t*)(ptr); |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) |
||||
{ |
||||
*(__packed uint32_t*)(ptr) = val;; |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__packed struct __iar_u32 { uint32_t v; }; |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) |
||||
#endif |
||||
|
||||
#ifndef __USED |
||||
#if __ICCARM_V8 |
||||
#define __USED __attribute__((used)) |
||||
#else |
||||
#define __USED _Pragma("__root") |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __WEAK |
||||
#if __ICCARM_V8 |
||||
#define __WEAK __attribute__((weak)) |
||||
#else |
||||
#define __WEAK _Pragma("__weak") |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__ |
||||
#define __ICCARM_INTRINSICS_VERSION__ 0 |
||||
#endif |
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2 |
||||
|
||||
#if defined(__CLZ) |
||||
#undef __CLZ |
||||
#endif |
||||
#if defined(__REVSH) |
||||
#undef __REVSH |
||||
#endif |
||||
#if defined(__RBIT) |
||||
#undef __RBIT |
||||
#endif |
||||
#if defined(__SSAT) |
||||
#undef __SSAT |
||||
#endif |
||||
#if defined(__USAT) |
||||
#undef __USAT |
||||
#endif |
||||
|
||||
#include "iccarm_builtin.h" |
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq |
||||
#define __disable_irq __iar_builtin_disable_interrupt |
||||
#define __enable_fault_irq __iar_builtin_enable_fiq |
||||
#define __enable_irq __iar_builtin_enable_interrupt |
||||
#define __arm_rsr __iar_builtin_rsr |
||||
#define __arm_wsr __iar_builtin_wsr |
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR")) |
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI")) |
||||
#define __get_CONTROL() (__arm_rsr("CONTROL")) |
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) |
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||||
#define __get_FPSCR() (__arm_rsr("FPSCR")) |
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) |
||||
#else |
||||
#define __get_FPSCR() ( 0 ) |
||||
#define __set_FPSCR(VALUE) ((void)VALUE) |
||||
#endif |
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR")) |
||||
#define __get_MSP() (__arm_rsr("MSP")) |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U) |
||||
#else |
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM")) |
||||
#endif |
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK")) |
||||
#define __get_PSP() (__arm_rsr("PSP")) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U) |
||||
#else |
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM")) |
||||
#endif |
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR")) |
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) |
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) |
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) |
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) |
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) |
||||
#endif |
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) |
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) |
||||
#endif |
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) |
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) |
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) |
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) |
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) |
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) |
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) |
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) |
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) |
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) |
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) |
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) |
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) |
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U) |
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) |
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) |
||||
#endif |
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) |
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) |
||||
|
||||
#define __NOP __iar_builtin_no_operation |
||||
|
||||
#define __CLZ __iar_builtin_CLZ |
||||
#define __CLREX __iar_builtin_CLREX |
||||
|
||||
#define __DMB __iar_builtin_DMB |
||||
#define __DSB __iar_builtin_DSB |
||||
#define __ISB __iar_builtin_ISB |
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB |
||||
#define __LDREXH __iar_builtin_LDREXH |
||||
#define __LDREXW __iar_builtin_LDREX |
||||
|
||||
#define __RBIT __iar_builtin_RBIT |
||||
#define __REV __iar_builtin_REV |
||||
#define __REV16 __iar_builtin_REV16 |
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val) |
||||
{ |
||||
return (int16_t) __iar_builtin_REVSH(val); |
||||
} |
||||
|
||||
#define __ROR __iar_builtin_ROR |
||||
#define __RRX __iar_builtin_RRX |
||||
|
||||
#define __SEV __iar_builtin_SEV |
||||
|
||||
#if !__IAR_M0_FAMILY |
||||
#define __SSAT __iar_builtin_SSAT |
||||
#endif |
||||
|
||||
#define __STREXB __iar_builtin_STREXB |
||||
#define __STREXH __iar_builtin_STREXH |
||||
#define __STREXW __iar_builtin_STREX |
||||
|
||||
#if !__IAR_M0_FAMILY |
||||
#define __USAT __iar_builtin_USAT |
||||
#endif |
||||
|
||||
#define __WFE __iar_builtin_WFE |
||||
#define __WFI __iar_builtin_WFI |
||||
|
||||
#if __ARM_MEDIA__ |
||||
#define __SADD8 __iar_builtin_SADD8 |
||||
#define __QADD8 __iar_builtin_QADD8 |
||||
#define __SHADD8 __iar_builtin_SHADD8 |
||||
#define __UADD8 __iar_builtin_UADD8 |
||||
#define __UQADD8 __iar_builtin_UQADD8 |
||||
#define __UHADD8 __iar_builtin_UHADD8 |
||||
#define __SSUB8 __iar_builtin_SSUB8 |
||||
#define __QSUB8 __iar_builtin_QSUB8 |
||||
#define __SHSUB8 __iar_builtin_SHSUB8 |
||||
#define __USUB8 __iar_builtin_USUB8 |
||||
#define __UQSUB8 __iar_builtin_UQSUB8 |
||||
#define __UHSUB8 __iar_builtin_UHSUB8 |
||||
#define __SADD16 __iar_builtin_SADD16 |
||||
#define __QADD16 __iar_builtin_QADD16 |
||||
#define __SHADD16 __iar_builtin_SHADD16 |
||||
#define __UADD16 __iar_builtin_UADD16 |
||||
#define __UQADD16 __iar_builtin_UQADD16 |
||||
#define __UHADD16 __iar_builtin_UHADD16 |
||||
#define __SSUB16 __iar_builtin_SSUB16 |
||||
#define __QSUB16 __iar_builtin_QSUB16 |
||||
#define __SHSUB16 __iar_builtin_SHSUB16 |
||||
#define __USUB16 __iar_builtin_USUB16 |
||||
#define __UQSUB16 __iar_builtin_UQSUB16 |
||||
#define __UHSUB16 __iar_builtin_UHSUB16 |
||||
#define __SASX __iar_builtin_SASX |
||||
#define __QASX __iar_builtin_QASX |
||||
#define __SHASX __iar_builtin_SHASX |
||||
#define __UASX __iar_builtin_UASX |
||||
#define __UQASX __iar_builtin_UQASX |
||||
#define __UHASX __iar_builtin_UHASX |
||||
#define __SSAX __iar_builtin_SSAX |
||||
#define __QSAX __iar_builtin_QSAX |
||||
#define __SHSAX __iar_builtin_SHSAX |
||||
#define __USAX __iar_builtin_USAX |
||||
#define __UQSAX __iar_builtin_UQSAX |
||||
#define __UHSAX __iar_builtin_UHSAX |
||||
#define __USAD8 __iar_builtin_USAD8 |
||||
#define __USADA8 __iar_builtin_USADA8 |
||||
#define __SSAT16 __iar_builtin_SSAT16 |
||||
#define __USAT16 __iar_builtin_USAT16 |
||||
#define __UXTB16 __iar_builtin_UXTB16 |
||||
#define __UXTAB16 __iar_builtin_UXTAB16 |
||||
#define __SXTB16 __iar_builtin_SXTB16 |
||||
#define __SXTAB16 __iar_builtin_SXTAB16 |
||||
#define __SMUAD __iar_builtin_SMUAD |
||||
#define __SMUADX __iar_builtin_SMUADX |
||||
#define __SMMLA __iar_builtin_SMMLA |
||||
#define __SMLAD __iar_builtin_SMLAD |
||||
#define __SMLADX __iar_builtin_SMLADX |
||||
#define __SMLALD __iar_builtin_SMLALD |
||||
#define __SMLALDX __iar_builtin_SMLALDX |
||||
#define __SMUSD __iar_builtin_SMUSD |
||||
#define __SMUSDX __iar_builtin_SMUSDX |
||||
#define __SMLSD __iar_builtin_SMLSD |
||||
#define __SMLSDX __iar_builtin_SMLSDX |
||||
#define __SMLSLD __iar_builtin_SMLSLD |
||||
#define __SMLSLDX __iar_builtin_SMLSLDX |
||||
#define __SEL __iar_builtin_SEL |
||||
#define __QADD __iar_builtin_QADD |
||||
#define __QSUB __iar_builtin_QSUB |
||||
#define __PKHBT __iar_builtin_PKHBT |
||||
#define __PKHTB __iar_builtin_PKHTB |
||||
#endif |
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ |
||||
#define __CLZ __cmsis_iar_clz_not_active |
||||
#define __SSAT __cmsis_iar_ssat_not_active |
||||
#define __USAT __cmsis_iar_usat_not_active |
||||
#define __RBIT __cmsis_iar_rbit_not_active |
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active |
||||
#endif |
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )) |
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active |
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active |
||||
#endif |
||||
|
||||
#ifdef __INTRINSICS_INCLUDED |
||||
#error intrinsics.h is already included previously! |
||||
#endif |
||||
|
||||
#include <intrinsics.h> |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ |
||||
#undef __CLZ |
||||
#undef __SSAT |
||||
#undef __USAT |
||||
#undef __RBIT |
||||
#undef __get_APSR |
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data) |
||||
{ |
||||
if (data == 0U) { return 32U; } |
||||
|
||||
uint32_t count = 0U; |
||||
uint32_t mask = 0x80000000U; |
||||
|
||||
while ((data & mask) == 0U) |
||||
{ |
||||
count += 1U; |
||||
mask = mask >> 1U; |
||||
} |
||||
return count; |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v) |
||||
{ |
||||
uint8_t sc = 31U; |
||||
uint32_t r = v; |
||||
for (v >>= 1U; v; v >>= 1U) |
||||
{ |
||||
r <<= 1U; |
||||
r |= v & 1U; |
||||
sc--; |
||||
} |
||||
return (r << sc); |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm("MRS %0,APSR" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )) |
||||
#undef __get_FPSCR |
||||
#undef __set_FPSCR |
||||
#define __get_FPSCR() (0) |
||||
#define __set_FPSCR(VALUE) ((void)VALUE) |
||||
#endif |
||||
|
||||
#pragma diag_suppress=Pe940 |
||||
#pragma diag_suppress=Pe177 |
||||
|
||||
#define __enable_irq __enable_interrupt |
||||
#define __disable_irq __disable_interrupt |
||||
#define __NOP __no_operation |
||||
|
||||
#define __get_xPSR __get_PSR |
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) |
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) |
||||
{ |
||||
return __LDREX((unsigned long *)ptr); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) |
||||
{ |
||||
return __STREX(value, (unsigned long *)ptr); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ |
||||
#if (__CORTEX_M >= 0x03) |
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value) |
||||
{ |
||||
uint32_t result; |
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); |
||||
return(result); |
||||
} |
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); |
||||
} |
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq |
||||
#define __disable_fault_irq __disable_fiq |
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */ |
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) |
||||
{ |
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); |
||||
} |
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ |
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ |
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if ((sat >= 1U) && (sat <= 32U)) |
||||
{ |
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); |
||||
const int32_t min = -1 - max ; |
||||
if (val > max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < min) |
||||
{ |
||||
return min; |
||||
} |
||||
} |
||||
return val; |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if (sat <= 31U) |
||||
{ |
||||
const uint32_t max = ((1U << sat) - 1U); |
||||
if (val > (int32_t)max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < 0) |
||||
{ |
||||
return 0U; |
||||
} |
||||
} |
||||
return (uint32_t)val; |
||||
} |
||||
#endif |
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ |
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) |
||||
{ |
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) |
||||
{ |
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) |
||||
{ |
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */ |
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) |
||||
{ |
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) |
||||
{ |
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) |
||||
{ |
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ |
||||
|
||||
#undef __IAR_FT |
||||
#undef __IAR_M0_FAMILY |
||||
#undef __ICCARM_V8 |
||||
|
||||
#pragma diag_default=Pe940 |
||||
#pragma diag_default=Pe177 |
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */ |
||||
@ -0,0 +1,39 @@
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h |
||||
* @brief CMSIS Core(M) Version definitions |
||||
* @version V5.0.2 |
||||
* @date 19. April 2017 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CMSIS_VERSION_H |
||||
#define __CMSIS_VERSION_H |
||||
|
||||
/* CMSIS Version definitions */ |
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ |
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ |
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ |
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,976 @@
@@ -0,0 +1,976 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h |
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File |
||||
* @version V1.0.0 |
||||
* @date 23. July 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC |
||||
#define __CORE_CM1_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex_M1 |
||||
@{ |
||||
*/ |
||||
|
||||
#include "cmsis_version.h" |
||||
|
||||
/* CMSIS CM1 definitions */ |
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */ |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TI_ARM__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT |
||||
#define __CORE_CM1_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM1_REV |
||||
#define __CM1_REV 0x0100U |
||||
#warning "__CM1_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex_M1 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
uint32_t RESERVED0; |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||||
\brief Type definitions for the System Control and ID Register not in the SCB |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t RESERVED0[2U]; |
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||||
} SCnSCB_Type; |
||||
|
||||
/* Auxiliary Control Register Definitions */ |
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ |
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ |
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ |
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M1 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Core Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL |
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
||||
#endif |
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ |
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ |
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ |
||||
#define NVIC_SetPriority __NVIC_SetPriority |
||||
#define NVIC_GetPriority __NVIC_GetPriority |
||||
#define NVIC_SystemReset __NVIC_SystemReset |
||||
#endif /* CMSIS_NVIC_VIRTUAL */ |
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL |
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
||||
#endif |
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetVector __NVIC_SetVector |
||||
#define NVIC_GetVector __NVIC_GetVector |
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */ |
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16 |
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */ |
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X) |
||||
#define __NVIC_GetPriorityGrouping() (0U) |
||||
|
||||
/**
|
||||
\brief Enable Interrupt |
||||
\details Enables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status |
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt is not enabled. |
||||
\return 1 Interrupt is enabled. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt |
||||
\details Disables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
__DSB(); |
||||
__ISB(); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
\note The priority cannot be set for every processor exception. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority |
||||
\details Encodes the priority for an interrupt with the given priority group, |
||||
preemptive priority value, and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0). |
||||
\param [in] SubPriority Subpriority value (starting from 0). |
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
return ( |
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
||||
); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority |
||||
\details Decodes an interrupt priority value with a given priority group to |
||||
preemptive priority value and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0). |
||||
\param [out] pSubPriority Subpriority value (starting from 0). |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector |
||||
\details Sets an interrupt vector in SRAM based interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
Address 0 must be mapped to SRAM. |
||||
\param [in] IRQn Interrupt number |
||||
\param [in] vector Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector |
||||
\details Reads an interrupt vector from interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions |
||||
\brief Function that provides FPU type. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief get FPU type |
||||
\details returns the FPU type |
||||
\returns |
||||
- \b 0: No FPU |
||||
- \b 1: Single precision FPU |
||||
- \b 2: Double + Single precision FPU |
||||
*/ |
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void) |
||||
{ |
||||
return 0U; /* No FPU */ |
||||
} |
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,87 +0,0 @@
@@ -1,87 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h |
||||
* @brief CMSIS Cortex-M Core Function Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMFUNC_H |
||||
#define __CORE_CMFUNC_H |
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
#endif /* __CORE_CMFUNC_H */ |
||||
@ -1,87 +0,0 @@
@@ -1,87 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h |
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMINSTR_H |
||||
#define __CORE_CMINSTR_H |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
#endif /* __CORE_CMINSTR_H */ |
||||
@ -1,96 +0,0 @@
@@ -1,96 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h |
||||
* @brief CMSIS Cortex-M SIMD Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMSIMD_H |
||||
#define __CORE_CMSIMD_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CMSIMD_H */ |
||||
@ -0,0 +1,270 @@
@@ -0,0 +1,270 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h |
||||
* @brief CMSIS MPU API for Armv7-M MPU |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef ARM_MPU_ARMV7_H |
||||
#define ARM_MPU_ARMV7_H |
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
* |
||||
* \param Region The region to be configured, number 0 to 15. |
||||
* \param BaseAddress The base address for the region. |
||||
*/ |
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \ |
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes |
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
||||
* \param IsShareable Region is shareable between multiple bus masters. |
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ |
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) |
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value |
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. |
||||
* \param SubRegionDisable Sub-region disable field. |
||||
* \param Size Region size of the region to be configured, for example 4K, 8K. |
||||
*/ |
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ |
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) |
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value |
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
||||
* \param IsShareable Region is shareable between multiple bus masters. |
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
||||
* \param SubRegionDisable Sub-region disable field. |
||||
* \param Size Region size of the region to be configured, for example 4K, 8K. |
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ |
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory. |
||||
* - TEX: 000b |
||||
* - Shareable |
||||
* - Non-cacheable |
||||
* - Non-bufferable |
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory. |
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable) |
||||
* - Shareable or non-shareable |
||||
* - Non-cacheable |
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable) |
||||
* |
||||
* \param IsShareable Configures the device memory as shareable or non-shareable. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory. |
||||
* - TEX: 1BBb (reflecting outer cacheability rules) |
||||
* - Shareable or non-shareable |
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules) |
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules) |
||||
* |
||||
* \param OuterCp Configures the outer cache policy. |
||||
* \param InnerCp Configures the inner cache policy. |
||||
* \param IsShareable Configures the memory as shareable or non-shareable. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_NOCACHE 0U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WB_WRA 1U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WT_NWA 2U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WB_NWA 3U |
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region |
||||
*/ |
||||
typedef struct { |
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t; |
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) |
||||
{ |
||||
MPU->RNR = rnr; |
||||
MPU->RASR = 0U; |
||||
} |
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register. |
||||
* \param rsar Value for RSAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) |
||||
{ |
||||
MPU->RBAR = rbar; |
||||
MPU->RASR = rasr; |
||||
} |
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rsar Value for RSAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) |
||||
{ |
||||
MPU->RNR = rnr; |
||||
MPU->RBAR = rbar; |
||||
MPU->RASR = rasr; |
||||
} |
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to. |
||||
* \param src Source data is copied from. |
||||
* \param len Amount of data words to be copied. |
||||
*/ |
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) |
||||
{ |
||||
uint32_t i; |
||||
for (i = 0U; i < len; ++i)
|
||||
{ |
||||
dst[i] = src[i]; |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; |
||||
while (cnt > MPU_TYPE_RALIASES) { |
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); |
||||
table += MPU_TYPE_RALIASES; |
||||
cnt -= MPU_TYPE_RALIASES; |
||||
} |
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); |
||||
} |
||||
|
||||
#endif |
||||
@ -0,0 +1,333 @@
@@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h |
||||
* @brief CMSIS MPU API for Armv8-M MPU |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef ARM_MPU_ARMV8_H |
||||
#define ARM_MPU_ARMV8_H |
||||
|
||||
/** \brief Attribute for device memory (outer only) */ |
||||
#define ARM_MPU_ATTR_DEVICE ( 0U ) |
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */ |
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) |
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data. |
||||
* \param WB Write-Back: Set to 1 to use write-back update policy. |
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. |
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. |
||||
*/ |
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ |
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) |
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) |
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) |
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U) |
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U) |
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes |
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes |
||||
*/ |
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) |
||||
|
||||
/** \brief Normal memory non-shareable */ |
||||
#define ARM_MPU_SH_NON (0U) |
||||
|
||||
/** \brief Normal memory outer shareable */ |
||||
#define ARM_MPU_SH_OUTER (2U) |
||||
|
||||
/** \brief Normal memory inner shareable */ |
||||
#define ARM_MPU_SH_INNER (3U) |
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory. |
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory. |
||||
*/ |
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) |
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. |
||||
* \param SH Defines the Shareability domain for this memory region. |
||||
* \param RO Read-Only: Set to 1 for a read-only memory region. |
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. |
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. |
||||
*/ |
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ |
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) |
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. |
||||
* \param IDX The attribute index to be associated with this memory region. |
||||
*/ |
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \ |
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk)) |
||||
|
||||
/**
|
||||
* Struct for a single MPU Region |
||||
*/ |
||||
typedef struct { |
||||
uint32_t RBAR; /*!< Region Base Address Register value */ |
||||
uint32_t RLAR; /*!< Region Limit Address Register value */ |
||||
} ARM_MPU_Region_t; |
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
#endif |
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured. |
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) |
||||
{ |
||||
const uint8_t reg = idx / 4U; |
||||
const uint32_t pos = ((idx % 4U) * 8U); |
||||
const uint32_t mask = 0xFFU << pos; |
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { |
||||
return; // invalid index
|
||||
} |
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); |
||||
} |
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) |
||||
{ |
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) |
||||
{ |
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); |
||||
} |
||||
#endif |
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used. |
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) |
||||
{ |
||||
mpu->RNR = rnr; |
||||
mpu->RLAR = 0U; |
||||
} |
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) |
||||
{ |
||||
ARM_MPU_ClrRegionEx(MPU, rnr); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) |
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr); |
||||
} |
||||
#endif |
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used. |
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
mpu->RNR = rnr; |
||||
mpu->RBAR = rbar; |
||||
mpu->RLAR = rlar; |
||||
} |
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
} |
||||
#endif |
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to. |
||||
* \param src Source data is copied from. |
||||
* \param len Amount of data words to be copied. |
||||
*/ |
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) |
||||
{ |
||||
uint32_t i; |
||||
for (i = 0U; i < len; ++i)
|
||||
{ |
||||
dst[i] = src[i]; |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used. |
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; |
||||
if (cnt == 1U) { |
||||
mpu->RNR = rnr; |
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); |
||||
} else { |
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); |
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; |
||||
|
||||
mpu->RNR = rnrBase; |
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { |
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset; |
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); |
||||
table += c; |
||||
cnt -= c; |
||||
rnrOffset = 0U; |
||||
rnrBase += MPU_TYPE_RALIASES; |
||||
mpu->RNR = rnrBase; |
||||
} |
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); |
||||
} |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
@ -0,0 +1,70 @@
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h |
||||
* @brief Context Management for Armv8-M TrustZone |
||||
* @version V1.0.1 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef TZ_CONTEXT_H |
||||
#define TZ_CONTEXT_H |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifndef TZ_MODULEID_T |
||||
#define TZ_MODULEID_T |
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t; |
||||
#endif |
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t; |
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void); |
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); |
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); |
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); |
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); |
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@ -0,0 +1,320 @@
@@ -0,0 +1,320 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_exti.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of EXTI HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_EXTI_H |
||||
#define STM32F1xx_HAL_EXTI_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief HAL EXTI common Callback ID enumeration definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_EXTI_COMMON_CB_ID = 0x00U |
||||
} EXTI_CallbackIDTypeDef; |
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Line; /*!< Exti line number */ |
||||
void (* PendingCallback)(void); /*!< Exti pending callback */ |
||||
} EXTI_HandleTypeDef; |
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */ |
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */ |
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */ |
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It |
||||
can be a value of @ref EXTI_GPIOSel */ |
||||
} EXTI_ConfigTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ |
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ |
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ |
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ |
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ |
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ |
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ |
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ |
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ |
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ |
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ |
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ |
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ |
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ |
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ |
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ |
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ |
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
||||
#if defined(EXTI_IMR_IM18) |
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ |
||||
#endif /* EXTI_IMR_IM18 */ |
||||
#if defined(EXTI_IMR_IM19) |
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ |
||||
#endif /* EXTI_IMR_IM19 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_MODE_NONE 0x00000000u |
||||
#define EXTI_MODE_INTERRUPT 0x00000001u |
||||
#define EXTI_MODE_EVENT 0x00000002u |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_TRIGGER_NONE 0x00000000u |
||||
#define EXTI_TRIGGER_RISING 0x00000001u |
||||
#define EXTI_TRIGGER_FALLING 0x00000002u |
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief |
||||
* @{ |
||||
*/ |
||||
#define EXTI_GPIOA 0x00000000u |
||||
#define EXTI_GPIOB 0x00000001u |
||||
#define EXTI_GPIOC 0x00000002u |
||||
#define EXTI_GPIOD 0x00000003u |
||||
#if defined (GPIOE) |
||||
#define EXTI_GPIOE 0x00000004u |
||||
#endif /* GPIOE */ |
||||
#if defined (GPIOF) |
||||
#define EXTI_GPIOF 0x00000005u |
||||
#endif /* GPIOF */ |
||||
#if defined (GPIOG) |
||||
#define EXTI_GPIOG 0x00000006u |
||||
#endif /* GPIOG */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private constants --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief EXTI Line property definition |
||||
*/ |
||||
#define EXTI_PROPERTY_SHIFT 24u |
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) |
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) |
||||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) |
||||
|
||||
/**
|
||||
* @brief EXTI bit usage |
||||
*/ |
||||
#define EXTI_PIN_MASK 0x0000001Fu |
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode |
||||
*/ |
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) |
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities |
||||
*/ |
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
||||
|
||||
/**
|
||||
* @brief EXTI Line number |
||||
*/ |
||||
#if defined(EXTI_IMR_IM19) |
||||
#define EXTI_LINE_NB 20UL |
||||
#elif defined(EXTI_IMR_IM18) |
||||
#define EXTI_LINE_NB 19UL |
||||
#else /* EXTI_IMR_IM17 */ |
||||
#define EXTI_LINE_NB 18UL |
||||
#endif /* EXTI_IMR_IM19 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ |
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) |
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ |
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) |
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) |
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) |
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) |
||||
|
||||
#if defined (GPIOG) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG)) |
||||
#elif defined (GPIOF) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF)) |
||||
#elif defined (GPIOE) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE)) |
||||
#else |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD)) |
||||
#endif /* GPIOG */ |
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions |
||||
* @{ |
||||
*/ |
||||
/* Configuration functions ****************************************************/ |
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); |
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); |
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions |
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); |
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_EXTI_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,559 @@
@@ -0,0 +1,559 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_exti.c |
||||
* @author MCD Application Team |
||||
* @brief EXTI HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral: |
||||
* + Initialization and de-initialization functions |
||||
* + IO operation functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### EXTI Peripheral features ##### |
||||
============================================================================== |
||||
[..] |
||||
(+) Each Exti line can be configured within this driver. |
||||
|
||||
(+) Exti line can be configured in 3 different modes |
||||
(++) Interrupt |
||||
(++) Event |
||||
(++) Both of them |
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers |
||||
(++) Rising |
||||
(++) Falling |
||||
(++) Both of them |
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different |
||||
interrupts pending registers which allow to distinguish which transition |
||||
occurs: |
||||
(++) Rising edge pending interrupt |
||||
(++) Falling |
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can |
||||
be selected through multiplexer. |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). |
||||
(++) Choose the interrupt line number by setting "Line" member from |
||||
EXTI_ConfigTypeDef structure. |
||||
(++) Configure the interrupt and/or event mode using "Mode" member from |
||||
EXTI_ConfigTypeDef structure. |
||||
(++) For configurable lines, configure rising and/or falling trigger |
||||
"Trigger" member from EXTI_ConfigTypeDef structure. |
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" |
||||
member from GPIO_InitTypeDef structure. |
||||
|
||||
(#) Get current Exti configuration of a dedicated line using |
||||
HAL_EXTI_GetConfigLine(). |
||||
(++) Provide exiting handle as parameter. |
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. |
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). |
||||
(++) Provide exiting handle as parameter. |
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). |
||||
(++) Provide exiting handle as first parameter. |
||||
(++) Provide which callback will be registered using one value from |
||||
EXTI_CallbackIDTypeDef. |
||||
(++) Provide callback function pointer. |
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending(). |
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending(). |
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI(). |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{ |
||||
*/ |
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out |
||||
* of bounds [0,3] in following API : |
||||
* HAL_EXTI_SetConfigLine |
||||
* HAL_EXTI_GetConfigLine |
||||
* HAL_EXTI_ClearConfigLine |
||||
*/ |
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private defines -----------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Configuration functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param pExtiConfig Pointer on EXTI configuration to be set. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line)); |
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); |
||||
|
||||
/* Assign line number to handle */ |
||||
hexti->Line = pExtiConfig->Line; |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* Configure triggers for configurable lines */ |
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); |
||||
|
||||
/* Configure rising trigger */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) |
||||
{ |
||||
EXTI->RTSR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->RTSR &= ~maskline; |
||||
} |
||||
|
||||
/* Configure falling trigger */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) |
||||
{ |
||||
EXTI->FTSR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->FTSR &= ~maskline; |
||||
} |
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */ |
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
AFIO->EXTICR[linepos >> 2u] = regval; |
||||
} |
||||
} |
||||
|
||||
/* Configure interrupt mode : read current mode */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) |
||||
{ |
||||
EXTI->IMR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->IMR &= ~maskline; |
||||
} |
||||
|
||||
/* Configure event mode : read current mode */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) |
||||
{ |
||||
EXTI->EMR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->EMR &= ~maskline; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param pExtiConfig Pointer on structure to store Exti configuration. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameter */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
|
||||
/* Store handle line number to configuration structure */ |
||||
pExtiConfig->Line = hexti->Line; |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* 1] Get core mode : interrupt */ |
||||
|
||||
/* Check if selected line is enable */ |
||||
if ((EXTI->IMR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT; |
||||
} |
||||
else |
||||
{ |
||||
pExtiConfig->Mode = EXTI_MODE_NONE; |
||||
} |
||||
|
||||
/* Get event mode */ |
||||
/* Check if selected line is enable */ |
||||
if ((EXTI->EMR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT; |
||||
} |
||||
|
||||
/* 2] Get trigger for configurable lines : rising */ |
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
/* Check if configuration of selected line is enable */ |
||||
if ((EXTI->RTSR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; |
||||
} |
||||
else |
||||
{ |
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; |
||||
} |
||||
|
||||
/* Get falling configuration */ |
||||
/* Check if configuration of selected line is enable */ |
||||
if ((EXTI->FTSR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; |
||||
} |
||||
|
||||
/* Get Gpio port selection for gpio lines */ |
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); |
||||
} |
||||
else |
||||
{ |
||||
pExtiConfig->GPIOSel = 0x00u; |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* No Trigger selected */ |
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; |
||||
pExtiConfig->GPIOSel = 0x00u; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if (hexti == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameter */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
|
||||
/* compute line mask */ |
||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* 1] Clear interrupt mode */ |
||||
EXTI->IMR = (EXTI->IMR & ~maskline); |
||||
|
||||
/* 2] Clear event mode */ |
||||
EXTI->EMR = (EXTI->EMR & ~maskline); |
||||
|
||||
/* 3] Clear triggers in case of configurable lines */ |
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline); |
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline); |
||||
|
||||
/* Get Gpio port selection for gpio lines */ |
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
AFIO->EXTICR[linepos >> 2u] = regval; |
||||
} |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param CallbackID User callback identifier. |
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. |
||||
* @param pPendingCbfn function pointer to be stored as callback. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
switch (CallbackID) |
||||
{ |
||||
case HAL_EXTI_COMMON_CB_ID: |
||||
hexti->PendingCallback = pPendingCbfn; |
||||
break; |
||||
|
||||
default: |
||||
status = HAL_ERROR; |
||||
break; |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field. |
||||
* @param hexti Exti handle. |
||||
* @param ExtiLine Exti line number. |
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_EXTI_LINE(ExtiLine)); |
||||
|
||||
/* Check null pointer */ |
||||
if (hexti == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
else |
||||
{ |
||||
/* Store line number as handle private field */ |
||||
hexti->Line = ExtiLine; |
||||
|
||||
return HAL_OK; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions. |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request. |
||||
* @param hexti Exti handle. |
||||
* @retval none. |
||||
*/ |
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t maskline; |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Get pending bit */ |
||||
regval = (EXTI->PR & maskline); |
||||
if (regval != 0x00u) |
||||
{ |
||||
/* Clear pending bit */ |
||||
EXTI->PR = maskline; |
||||
|
||||
/* Call callback */ |
||||
if (hexti->PendingCallback != NULL) |
||||
{ |
||||
hexti->PendingCallback(); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @param Edge Specify which pending edge as to be checked. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
||||
* This parameter is kept for compatibility with other series. |
||||
* @retval 1 if interrupt is pending else 0. |
||||
*/ |
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t maskline; |
||||
uint32_t linepos; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* return 1 if bit is set else 0 */ |
||||
regval = ((EXTI->PR & maskline) >> linepos); |
||||
return regval; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @param Edge Specify which pending edge as to be clear. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
||||
* This parameter is kept for compatibility with other series. |
||||
* @retval None. |
||||
*/ |
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
||||
{ |
||||
uint32_t maskline; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Clear Pending bit */ |
||||
EXTI->PR = maskline; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @retval None. |
||||
*/ |
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t maskline; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Generate Software interrupt */ |
||||
EXTI->SWIER = maskline; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,231 +0,0 @@
@@ -1,231 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_spi_ex.c |
||||
* @author MCD Application Team |
||||
* @brief Extended SPI HAL module driver. |
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities SPI extension peripheral: |
||||
* + Extended Peripheral Control functions |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup SPI
|
||||
* @{ |
||||
*/ |
||||
#ifdef HAL_SPI_MODULE_ENABLED |
||||
|
||||
/** @defgroup SPI_Private_Variables SPI Private Variables
|
||||
* @{ |
||||
*/ |
||||
#if (USE_SPI_CRC != 0U) |
||||
/* Variable used to determine if device is impacted by implementation of workaround
|
||||
related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: |
||||
- STM32F101CDE/STM32F103CDE |
||||
- Revision ID : Z |
||||
- SPI2 |
||||
- In receive only mode, with CRC calculation enabled, at the end of the CRC reception, |
||||
the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: |
||||
+ If the value is 0, the complete data transfer is successful. |
||||
+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. |
||||
If CRCERR is found reset, the complete data transfer is considered successful. |
||||
*/ |
||||
uint8_t uCRCErrorWorkaroundCheck = 0U; |
||||
#endif /* USE_SPI_CRC */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initializes the SPI according to the specified parameters
|
||||
* in the SPI_InitTypeDef and create the associated handle. |
||||
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
||||
* the configuration information for SPI module. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) |
||||
{ |
||||
/* Check the SPI handle allocation */ |
||||
if(hspi == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
||||
assert_param(IS_SPI_MODE(hspi->Init.Mode)); |
||||
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); |
||||
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); |
||||
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); |
||||
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); |
||||
assert_param(IS_SPI_NSS(hspi->Init.NSS)); |
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); |
||||
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); |
||||
|
||||
#if (USE_SPI_CRC != 0U) |
||||
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); |
||||
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
||||
{ |
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); |
||||
} |
||||
#else |
||||
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
||||
#endif /* USE_SPI_CRC */ |
||||
|
||||
if(hspi->State == HAL_SPI_STATE_RESET) |
||||
{ |
||||
/* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
||||
HAL_SPI_MspInit(hspi); |
||||
} |
||||
|
||||
hspi->State = HAL_SPI_STATE_BUSY; |
||||
|
||||
/* Disble the selected SPI peripheral */ |
||||
__HAL_SPI_DISABLE(hspi); |
||||
|
||||
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ |
||||
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
||||
Communication speed, First bit and CRC calculation state */ |
||||
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | |
||||
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | |
||||
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); |
||||
|
||||
/* Configure : NSS management */ |
||||
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); |
||||
|
||||
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/ |
||||
/* Configure : CRC Polynomial */ |
||||
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); |
||||
|
||||
#if defined(SPI_I2SCFGR_I2SMOD) |
||||
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ |
||||
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); |
||||
#endif /* SPI_I2SCFGR_I2SMOD */ |
||||
|
||||
#if (USE_SPI_CRC != 0U) |
||||
#if defined (STM32F101xE) || defined (STM32F103xE) |
||||
/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
|
||||
CRC errors wrongly detected */ |
||||
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
|
||||
Revision ID information is only available in Debug mode, so Workaround could not be implemented |
||||
to distinguish Rev Z devices (issue present) from more recent version (issue fixed). |
||||
So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ |
||||
uCRCErrorWorkaroundCheck = 0U; |
||||
#else |
||||
uCRCErrorWorkaroundCheck = 0U; |
||||
#endif /* STM32F101xE || STM32F103xE */ |
||||
#endif /* USE_SPI_CRC */ |
||||
|
||||
hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
||||
hspi->State = HAL_SPI_STATE_READY; |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup SPI_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
#if (USE_SPI_CRC != 0U) |
||||
/**
|
||||
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
|
||||
* according to SPI instance, Device type, and revision ID. |
||||
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
||||
* the configuration information for SPI module. |
||||
* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
|
||||
*/ |
||||
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) |
||||
{ |
||||
#if defined(STM32F101xE) || defined(STM32F103xE) |
||||
/* Check how to handle this CRC error (workaround to be applied or not) */ |
||||
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ |
||||
if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2)) |
||||
{ |
||||
if(hspi->Instance->RXCRCR == 0U) |
||||
{ |
||||
return (SPI_INVALID_CRC_ERROR); |
||||
} |
||||
} |
||||
return (SPI_VALID_CRC_ERROR); |
||||
#else |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(hspi); |
||||
|
||||
return (SPI_VALID_CRC_ERROR); |
||||
#endif |
||||
} |
||||
#endif /* USE_SPI_CRC */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,88 +0,0 @@
@@ -1,88 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : dma.h |
||||
* Description : This file contains all the function prototypes for |
||||
* the dma.c file |
||||
****************************************************************************** |
||||
* This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* Copyright (c) 2018 STMicroelectronics International N.V.
|
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted, provided that the following conditions are met: |
||||
* |
||||
* 1. Redistribution of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific written permission. |
||||
* 4. This software, including modifications and/or derivative works of this
|
||||
* software, must execute solely and exclusively on microcontroller or |
||||
* microprocessor devices manufactured by or for STMicroelectronics. |
||||
* 5. Redistribution and use of this software other than as permitted under
|
||||
* this license is void and will automatically terminate your rights under
|
||||
* this license.
|
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY |
||||
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
|
||||
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __dma_H |
||||
#define __dma_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* DMA memory to memory transfer handles -------------------------------------*/ |
||||
extern void _Error_Handler(char*, int); |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_DMA_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __dma_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -1,88 +0,0 @@
@@ -1,88 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : gpio.h |
||||
* Description : This file contains all the functions prototypes for
|
||||
* the gpio
|
||||
****************************************************************************** |
||||
* This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* Copyright (c) 2018 STMicroelectronics International N.V.
|
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted, provided that the following conditions are met: |
||||
* |
||||
* 1. Redistribution of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific written permission. |
||||
* 4. This software, including modifications and/or derivative works of this
|
||||
* software, must execute solely and exclusively on microcontroller or |
||||
* microprocessor devices manufactured by or for STMicroelectronics. |
||||
* 5. Redistribution and use of this software other than as permitted under
|
||||
* this license is void and will automatically terminate your rights under
|
||||
* this license.
|
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY |
||||
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
|
||||
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __gpio_H |
||||
#define __gpio_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_GPIO_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ pinoutConfig_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -1,90 +0,0 @@
@@ -1,90 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file : main.h |
||||
* @brief : Header for main.c file. |
||||
* This file contains the common defines of the application. |
||||
****************************************************************************** |
||||
* This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* Copyright (c) 2018 STMicroelectronics International N.V.
|
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted, provided that the following conditions are met: |
||||
* |
||||
* 1. Redistribution of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific written permission. |
||||
* 4. This software, including modifications and/or derivative works of this
|
||||
* software, must execute solely and exclusively on microcontroller or |
||||
* microprocessor devices manufactured by or for STMicroelectronics. |
||||
* 5. Redistribution and use of this software other than as permitted under
|
||||
* this license is void and will automatically terminate your rights under
|
||||
* this license.
|
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY |
||||
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
|
||||
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __MAIN_H__ |
||||
#define __MAIN_H__ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
|
||||
#define LED_Pin GPIO_PIN_13 |
||||
#define LED_GPIO_Port GPIOC |
||||
#define TEST_Pin GPIO_PIN_0 |
||||
#define TEST_GPIO_Port GPIOA |
||||
|
||||
/* ########################## Assert Selection ############################## */ |
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code |
||||
*/ |
||||
/* #define USE_FULL_ASSERT 1U */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
void _Error_Handler(char *, int); |
||||
|
||||
#define Error_Handler() _Error_Handler(__FILE__, __LINE__) |
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __MAIN_H__ */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -1,91 +0,0 @@
@@ -1,91 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : SPI.h |
||||
* Description : This file provides code for the configuration |
||||
* of the SPI instances. |
||||
****************************************************************************** |
||||
* This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* Copyright (c) 2018 STMicroelectronics International N.V.
|
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted, provided that the following conditions are met: |
||||
* |
||||
* 1. Redistribution of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific written permission. |
||||
* 4. This software, including modifications and/or derivative works of this
|
||||
* software, must execute solely and exclusively on microcontroller or |
||||
* microprocessor devices manufactured by or for STMicroelectronics. |
||||
* 5. Redistribution and use of this software other than as permitted under
|
||||
* this license is void and will automatically terminate your rights under
|
||||
* this license.
|
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY |
||||
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
|
||||
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __spi_H |
||||
#define __spi_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern SPI_HandleTypeDef hspi1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
|
||||
void MX_SPI1_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ spi_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -1,68 +0,0 @@
@@ -1,68 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_it.h |
||||
* @brief This file contains the headers of the interrupt handlers. |
||||
****************************************************************************** |
||||
* |
||||
* COPYRIGHT(c) 2018 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_IT_H |
||||
#define __STM32F1xx_IT_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
#include "main.h" |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* Exported functions ------------------------------------------------------- */ |
||||
|
||||
void NMI_Handler(void); |
||||
void HardFault_Handler(void); |
||||
void MemManage_Handler(void); |
||||
void BusFault_Handler(void); |
||||
void UsageFault_Handler(void); |
||||
void SVC_Handler(void); |
||||
void DebugMon_Handler(void); |
||||
void PendSV_Handler(void); |
||||
void SysTick_Handler(void); |
||||
void DMA1_Channel3_IRQHandler(void); |
||||
void USB_LP_CAN1_RX0_IRQHandler(void); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_IT_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -1,114 +0,0 @@
@@ -1,114 +0,0 @@
|
||||
/**
|
||||
****************************************************************************** |
||||
* @file : usb_device.h |
||||
* @version : v2.0_Cube |
||||
* @brief : Header for usb_device.c file. |
||||
****************************************************************************** |
||||
* This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* Copyright (c) 2018 STMicroelectronics International N.V.
|
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted, provided that the following conditions are met: |
||||
* |
||||
* 1. Redistribution of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of other
|
||||
* contributors to this software may be used to endorse or promote products
|
||||
* derived from this software without specific written permission. |
||||
* 4. This software, including modifications and/or derivative works of this
|
||||
* software, must execute solely and exclusively on microcontroller or |
||||
* microprocessor devices manufactured by or for STMicroelectronics. |
||||
* 5. Redistribution and use of this software other than as permitted under
|
||||
* this license is void and will automatically terminate your rights under
|
||||
* this license.
|
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY |
||||
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
|
||||
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __USB_DEVICE__H__ |
||||
#define __USB_DEVICE__H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx.h" |
||||
#include "stm32f1xx_hal.h" |
||||
#include "usbd_def.h" |
||||
|
||||
/* USER CODE BEGIN INCLUDE */ |
||||
|
||||
/* USER CODE END INCLUDE */ |
||||
|
||||
/** @addtogroup USBD_OTG_DRIVER
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup USBD_DEVICE USBD_DEVICE
|
||||
* @brief Device file for Usb otg low level driver. |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables
|
||||
* @brief Public variables. |
||||
* @{ |
||||
*/ |
||||
|
||||
/** USB device core handle. */ |
||||
extern USBD_HandleTypeDef hUsbDeviceFS; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype
|
||||
* @brief Declaration of public functions for Usb device. |
||||
* @{ |
||||
*/ |
||||
|
||||
/** USB Device initialization function. */ |
||||
void MX_USB_DEVICE_Init(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __USB_DEVICE__H__ */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue